[2507.04736] ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning

Computer Science > Artificial Intelligence arXiv:2507.04736 (cs) [Submitted on 7 Jul 2025 (v1), last revised 10 Apr 2026 (this version, v2)] Title:ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning Authors:Zhirong Chen, Kaiyan Chang, Zhuolin Li, Cangyuan Li, Xinyang He, Chujie Chen, Mengdi Wang, Haobo Xu, Yinhe Han, Huawei Li, Ying Wang View a PDF of the paper titled ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning, by Zhirong Chen and 10 other authors View PDF HTML (experimental) Abstract:Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically fail to simultaneously optimize functional correctness and hardware efficiency metrics such as Power, Performance, and Area (PPA). Methods relying on supervised fine-tuning commonly produce functionally correct but suboptimal designs due to the lack of inherent mechanisms for learning hardware optimization principles. Conversely, external post-processing techniques aiming to refine PPA performance after generation often suffer from inefficiency and do not improve the LLMs' intrinsic capabilities. To overcome these challenges, we propose ChipSeek, a novel hierarchical reward based reinforcement learning framework designed to encourage LLMs to generate RTL code that is both functionally correct and optimized for PPA metrics. Our approach integrates ...