[2603.19347] Exploring the Agentic Frontier of Verilog Code Generation

Computer Science > Hardware Architecture arXiv:2603.19347 (cs) [Submitted on 19 Mar 2026] Title:Exploring the Agentic Frontier of Verilog Code Generation Authors:Patrick Yubeaton, Chinmay Hegde, Siddharth Garg View a PDF of the paper titled Exploring the Agentic Frontier of Verilog Code Generation, by Patrick Yubeaton and 2 other authors View PDF HTML (experimental) Abstract:Large language models (LLMs) have made rapid advancements in code generation for popular languages such as Python and C++. Many of these recent gains can be attributed to the use of ``agents'' that wrap domain-relevant tools alongside LLMs. Hardware design languages such as Verilog have also seen improved code generation in recent years, but the impact of agentic frameworks on Verilog code generation tasks remains unclear. In this work, we present the first systematic evaluation of agentic LLMs for Verilog generation, using the recently introduced CVDP benchmark. We also introduce several open-source hardware design agent harnesses, providing a model-agnostic baseline for future work. Through controlled experiments across frontier models, we study how structured prompting and tool design affect performance, analyze agent failure modes and tool usage patterns, compare open-source and closed-source models, and provide qualitative examples of successful and failed agent runs. Our results show that naive agentic wrapping around frontier models can degrade performance (relative to standard forward passes wi...