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[2602.16442] Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA
Summary
The paper presents a hardware-accelerated graph neural network approach for neuromorphic event-based audio classification and keyword spotting, demonstrating significant efficiency and accuracy improvements on SoC FPGA.
Why It Matters
As data from embedded edge sensors grows, efficient processing methods become crucial. This research highlights a novel FPGA implementation that balances performance with energy efficiency, addressing the increasing demand for low-latency audio processing in various applications.
Key Takeaways
- The proposed architecture achieves competitive accuracy with significantly fewer parameters compared to existing models.
- It demonstrates a 95% word-end detection accuracy with low latency and power consumption.
- The implementation showcases the first end-to-end FPGA solution for event-driven keyword spotting.
Computer Science > Machine Learning arXiv:2602.16442 (cs) [Submitted on 18 Feb 2026] Title:Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA Authors:Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut, Hiroshi Nakano, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Thomas Dalgaty, Tomasz Kryjak View a PDF of the paper titled Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA, by Kamil Jeziorek and Piotr Wzorek and Krzysztof Blachut and Hiroshi Nakano and Manon Dampfhoffer and Thomas Mesquida and Hiroaki Nishi and Thomas Dalgaty and Tomasz Kryjak View PDF HTML (experimental) Abstract:As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a growing need for hardware-aware neural architectures that enable efficient, low-latency, and energy-conscious local processing. We present an FPGA implementation of event-graph neural networks for audio processing. We utilise an artificial cochlea that converts time-series signals into sparse event data, reducing memory and computation costs. Our architecture was implemented on a SoC FPGA and evaluated on two open-source datasets. For classification task, our baseline floating-point model achieves 92.7% accuracy on SHD dataset - only 2.4% below the s...
