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[2506.15316] J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor
Summary
The paper presents J3DAI, a compact DNN-based hardware accelerator designed for 3D-stacked CMOS image sensors, emphasizing its efficiency in edge AI applications.
Why It Matters
As edge AI technology becomes increasingly vital for real-time data processing, innovations like J3DAI are essential for enabling efficient, low-latency AI solutions in resource-constrained environments. This research highlights advancements in hardware architecture that can significantly impact various applications, including image classification and segmentation.
Key Takeaways
- J3DAI integrates a DNN accelerator within a 3-layer 3D-stacked CMOS image sensor.
- The design focuses on optimizing Performance-Power-Area (PPA) for edge AI tasks.
- Aidge software framework supports efficient programming and post-training quantization.
- Experimental results demonstrate J3DAI's versatility in handling diverse AI tasks.
- Future work aims to further optimize the architecture and explore new applications.
Computer Science > Hardware Architecture arXiv:2506.15316 (cs) [Submitted on 18 Jun 2025 (v1), last revised 20 Feb 2026 (this version, v2)] Title:J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor Authors:Benoit Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jerome Chossat, Pascal Pierunek, Pascal Vivet, Sebastien Thuries View a PDF of the paper titled J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor, by Benoit Tain and 11 other authors View PDF Abstract:This paper presents J3DAI, a tiny deep neural network-based hardware accelerator for a 3-layer 3D-stacked CMOS image sensor featuring an artificial intelligence (AI) chip integrating a Deep Neural Network (DNN)-based accelerator. The DNN accelerator is designed to efficiently perform neural network tasks such as image classification and segmentation. This paper focuses on the digital system of J3DAI, highlighting its Performance-Power-Area (PPA) characteristics and showcasing advanced edge AI capabilities on a CMOS image sensor. To support hardware, we utilized the Aidge comprehensive software framework, which enables the programming of both the host processor and the DNN accelerator. Aidge supports post-training quantization, significantly reducing memory footprint and computational complexity, making it crucial for deploying models on resource-constrained hardware like J3DAI. Our experimen...