[2603.29913] SISA: A Scale-In Systolic Array for GEMM Acceleration

Computer Science > Hardware Architecture arXiv:2603.29913 (cs) [Submitted on 31 Mar 2026] Title:SISA: A Scale-In Systolic Array for GEMM Acceleration Authors:Luigi Altamura, Alessio Cicero, Mateo Vázquez Maceiras, Mohammad Ali Maleki, Pedro Trancoso View a PDF of the paper titled SISA: A Scale-In Systolic Array for GEMM Acceleration, by Luigi Altamura and 4 other authors View PDF HTML (experimental) Abstract:The currently dominant AI/ML workloads, such as Large Language Models (LLMs), rely on the efficient execution of General Matrix-Matrix Multiplication (GEMM) operations. Thus, most systems are equipped with dedicated matrix hardware accelerators based on square Systolic Arrays (SAs) of Processing Elements (PEs). While this organization was effective for traditional Deep Neural Networks (DNNs), LLMs introduce input-dependent and highly skewed matrices, leading to underutilized SA resources. To address this challenge, we propose SISA (Scale-In Systolic Array), a novel SA architecture that partitions the traditional square array into horizontal rectangular slabs. With minimal overhead, SISA exposes parallelism through independently scheduled slabs for efficient execution of small or skewed matrix shapes, while retaining full-array operation for large GEMMs. SISA achieves up to 8.52x speedup and 93% energy-delay-product (EDP) reduction for representative LLMs compared to a state-of-the-art monolithic SA with the same number of PEs. Subjects: Hardware Architecture (cs.AR); A...